The practical activity status is available aici.
Introduction.
Combinational design using Verilog.
Using always and initial. Writing test benches.
Building a hierarchical design in Verilog. Simulating Verilog with Icarus Verilog. Laboratory 5 problems
Register files. Laboratory 6 problems
Datapath of the input preprocessing unit for a cryptographic application.
Control unit of the input preprocessing unit for a cryptographic application.
Message scheduler of a cryptographic application.
One Hot Encoding for FSMs. Simulating Verilog with Modelsim Altera Starter Edition.
CORDIC method.
CORDIC hardware design.
Flavius Opritoiu
Last edited:
Sunday, 25 September, 2016