The final marks for the practical laboratory activity are available here.
Additional exercises are available here.
Introduction.
Combinational circuits modeling using hardware description languages.
Using structured procedures for modeling synchronous sequential designs. Building a hierarchical design using hardware description languages.
Writing testbenches. Simulating Verilog with Modelsim Altera Starter Edition.
Designing of parameterized modules using Verilog.
Hardware description language constructs for multiple instantiations.
Interfacing digital components for data transfer.
Structures for iterated addition.
One Hot encoding for FSM implementation.
Error detection architectures.
The CORDIC method.
The hardware design of a CORDIC unit.
Materials for the practical activity laboratories, Fall 2016.
Flavius Opritoiu
Last edited:
Monday, 26 September, 2017