Laboratory projects

The projects that can be selected are described below. They are realized individually or in teams of up to 2 students depending on project's complexity.

1. Structured test architectures :
   • Concurrent error detection: implementation of a code-based error detection strategy.
   • IEEE 1149.1 design : implementing components of the Boundary Scan standard
     • TAP controller
     • Boundary Scan Cell
     • Instruction Register
     • custom instructions
   • IEEE 1149.1 usage : system integration of the JTAG standard
     • integrate the IEEE 1149.1 into new or existing digital system (including the required interface with a dedicated tester)
     • designing the test process for an existing IEEE 1149.1 enabled device
     • digital forensics using the IEEE 1149.1
     • fault attacks on IEEE 1149.1
   • IEEE 1149.1 interconnect : integrating the JTAG interface of several components
     • interconnect architectures
     • test process generation
   • Scan-based system testing : designing the test architecture for scan-based methods
     • Level Sensitive Scan Design
     • Scan-Set Logic
     • Scan Path
     • Random Access Scan
     • Input-Output Scan
   • BIST : adapt a Built-In Self-Test approach for an existing design
     • Built-In Logic Block Observer
     • Circular BILBO
     • Scan-based BIST
2. Memory testing:
   • Implement a specific RAM test algorithms
     • MASEST
     • MARCH
     • WALKPAT
     • GALPAT
     • GALCOL
3. Fault modeling :
   • Verilog fault modeling : implementation of Verilog PLI routines for injecting faults (gate-level faults, transistor-level faults) into a design, for fault simulation and fault detection rate evaluation.
   • Stuck-at Automatic Test Pattern Generator: implementation of an ATPG algorithm for the stuck-at fault model
     • Poage,
     • Poage-McCluskey
     • FAN
     • PODEM
     • Boolean satisfiability-based ATPG algorithms
   • Bridging faults Automatic Test Pattern Generator: implementation of an ATPG algorithm for the bridging fault model
   • Delay faults Automatic Test Pattern Generator: implementation of an ATPG algorithm for the delay fault model
4. Test project proposed by the team members.