Create a Modelsim Project

Open new project window

File -> New -> Project ...

Select project location and name

Chose a name for the project and a location.
Click OK.

Close "Add item to the project" window

Close window.

Add a new source file to the project

Important: Each module will be defined in its own source file. The module's source filename needs to coincide with the module's name!
In the newly opened Project window right-click and select Add to Project -> New File. If the Project window is not visible it can be opened from the View->Workspace menu.

Create new source file

Enter a name for the new source file.
Select source's fyletype (Verilog).
Click OK.

Write HDL code

Double click on the newly saved source file in the project window.
Write the code for the source file.
Don't forget to save regularly.