An RTL implementation of an arithmetic algorithm like Robertson, Booth (for arithmetic multiplication) or restoring/non-restoring division contains some components like:

• shift registers with parallel load capability: - they will be implemented behaviorally
• an ALU - implemented also behaviorally. It can be implemented using conversion functions/procedures that convert integer numbers to/from bit vectors (the code can be taken from "A VHDL cookbook", by Peter Ashenden, available online)
• maybe other parts, like gates, flip-flops, etc.
• A control unit (CU), implemented also behaviourally. The CU gives the commands (i.e. load, shift, etc) for the other components. The CU actually implements the algorithm, hence a good test for the CU would be an implementation that performs also the logic and arithmetic operations (like shift, addition, subtraction, etc). However, in the final version of the assignment, the CU will only give the commands to the other elements (registers, ALU, etc), but it will not perform the operations themselves.

At the end, the components should work together. A special care should be given to the synchronization between different components, i.e., if each component has been tested separately and all of them worked properly, but the entire system does not work properly, it is most likely a problem of synchronization.

The VHDL model will be tested by giving several sets of operands and checking the results.

Bonus points will be given for the accuracy of the implementation and for its capability to be generalized (e.g., to parametrize the number of bits for the binary representation of the operands).