- Lab 1 Simulate the VHDL code for the parity generator example. From the
configuration cfg_test OF test_b you can select which architecture of the parity_circ you want to simulate. The code is below:
The gates used for
the structural description
The entity
parity_circ with 3 architectures
Behavioural
model of the parity circuit
The test bench
for the parity circuit
- Lab 2 Counter and clock generator
Specification: make a VHDL description of a counter. When the input
reset is NOT zero, the counter either increments its integer-type
output at each rising edge of the clock signal (if the
input load is '0'), or it loads the value from its INTEGER type
input named parallel_in, if load='1'.
The code for the clock generator, the counter and the test bench is below:
Clock and reset generator
Clock and reset generator
for EDA Playgrounds: the process which generates the clock signal is suspended after it is
executed a number of times.
A counter
A test bench for the
counter
Requirements:
- Modify the counter such that:
- it will count in a cyclic manner, modulo MAX_VAL.
- the counter will activate a BIT type value named ovr each type when the value of the output goes from MAX_VAL-1 to 0 (zero).
- The counter will be able to count in both increasing and
decreasing order.
- Connect two counters, such that the ovr output of the
first counter will trigger the second counter.
- Realize a VHDL description of a shift-register. The data input and
output of the shift_register will be bit vectors of a given size (e.g.
BIT_VECTOR(7 DOWNTO 0) ). The register has also the folowing BIT type
inputs: clock, reset, right_shift_cmd (or left_shift_cmd),
serial_in, and a BIT type output named serial_out. Test the
shift register, inclusiverly by connecting serially two shift registers.
- Lab 3 Wait statements: simulate the code below, which describe different type of
WAIT statements.
The file w.vhd
Model in VHDL a D latch, a D flip-flop, a J-K flip-flop and a T
flip-flop.
- Lab 4 Use the code below, which contains an exemple of a
function that adds two bit vectors, in order to model an adder-subtracter circuit called AddSub,
which adds or subtracts two BIT_VECTOR operands
The package containing the function sum
Exemple of using the function sum
The files which contain the entity AddSub and the test bench for this entity:
The entity AddSub
The file containing the test bench (incomplete)
- Lab 5 Start Omnet++ . Go to directory where is installed the OMNeT++, then go to
sub-directory doc. From Tutorials, go to TicToc tutorial. Try to read and run as much
as possible from the TicToc tutorial, ideally from part 1 (Getting started) until Part 5 (Adding
Statistics Collection), including part 5.