A brief introduction to VHDL

General aspects

• VHDL is a Hardware Description Language (HDL)
• There are other HDLs, for example Verilog. VHDL and Verilog have very similar capabilities, but they differ in their syntax and, sometimes, in their philosophy.
• VHDL is a very powerful HDL, which contains features specific to:
  • high-level programming languages: types, subtypes, IF statement, LOOP statement, subprograms, etc
  • hardware description languages: simulation time, simulation mechanism, signals, ports, components, structural descriptions
• VHDL is a very complex programming language, and we do not intend to study VHDL in extenso at the Digital Logic laboratory.
• Our goal is to give you the basic notions of VHDL, that will allow you to simulate the circuits that we study at Digital Logic.
• In this way, VHDL will be a valuable tool in the process of studying the principles and the practical aspects of Digital Logic.
• We will illustrate the basic notions of VHDL using the multiplexer circuit described in Figures 13, 14 and 15, the first lecture.

Entity

• Each circuit that is modeled in VHDL must have an ENTITY declaration, or, in short, entity
• An entity declaration begins with the keyword ENTITY followed by the name of the entity and by the interface with the outside world
• An entity is like a black-box description: it specifies only the name of the circuit and its interface.
• The name of our entity is mux2_1, because we describe a multiplexer (mux) with 2 data inputs (called a and b), and one output, called z. There is another input, called s, whcih is the selection input (will be expalined).
• The interface of an entity consists of GENERIC parameters and PORTs.
• Generic parameters:
  • A generic is like a global constant, i.e, it is seen by all architectures of an entity
  • But, unlike a CONSTANT, a GENERIC can be modified when the entity is a component of a bigger design
  • In this example, the generic parameter is called delay, is of type TIME, and is initialized with the value 20 ns (nano seconds).
  • The most frequent utilization of generic parameters is for specifying circuit delays.
  • In VHDL, TIME is a predefined type, called a physical type, because it has measure units. The measure units for time start from fs (femto-seconds) to hr (hours)
  • At Digital Logic we will work with time intervals expressed usually in nano-seconds (ns).
• Ports:
  • A port has a mode and a type
  • The ports of an entity are either input ports, having the mode IN, or output ports, having the mode OUT.
  • In VHDL a port can have a bidirectional mode (either INOUT, or BUFFER), but we don't discuss this aspect here.
  • All ports of entity mux2_1 are of type BIT, but in VHDL a port can have (almost) any type
  • Type BIT is predefined in VHDL and has the values '0' and '1'.
  • The value '0' corresponds to logic zero, while the value '1' means logic one.
  • Ports belong to the class SIGNAL. In VHDL there is a clear distinction between signals and variables:
    • A variable has only one value at a moment, like in any programming language.
    • A signal consists of a series of values and the time moments when the signal takes each of these values. It is like a real-life signals that we can see on an osciloscope.
    • The signals in VHDL are either ports of entities, or internal signals which interconnect different parts of a design.
• The entity declaration ends with the keyword END optionally followed by the keyword ENTITY and, also optionally, by the name of the entity

Architecture body

• An entity doesn't do anything by itself
• In order to specify what an entity does or how it is implemented, we need an ARCHITECTURE BODY (or, simply, ARCHITECTURE)
• An entity can have any number of architecure bodies !!
• VHDL is a concurrent language because the hardware works concurrently, but there are "regions" with sequential code: inside process statements and inside subprograms
• Concurrent means that all statements are executed in the same time, hence the order in which they are written is not important
• Sequential means that the statements are executed one by one, in the order in which they are written
• After the keyword ARCHITECTURE we have the name of the architecture and the name of the corresponding entity. Here, the name of the architecture is behave, because it is a behavioural description.
• Then it follows the declaration part of the architecture, before the keyword BEGIN
• Between the keywords BEGIN and END [ARCHITECTURE] there is the body of the architecture
• Here the symbol [ ] means optional
• The statements situated in the architecture body are concurrent

Modelling styles in VHDL

• Hence, in VHDL we can have behavioural modelling (called also sequential modelling style), and structural modelling style (like a circuit diagram), and there also a third modelling style, called dataflow modelling.

  Behavioural descriptions

  • A behavioural description of a circuit or of a system describes the behaviour of the circuit, without paying attention to its structure.
  • A behavioural description is a high-level description of a circuit, being more abstract than a structural description of the same circuit.
  • Behavioural description means with processes.
  • The statement PROCESS is a composed statement.
  • The statement PROCESS itself is a concurrent statement, but the statements inside the PROCESS (between BEGIN and END PROCESS) execute sequentially.
  • At Digital Logic we will show a behavioural description of a multiplexer, but in general we will use more often the structural and data-flow styles of modelling.

  Structural descriptions

  • In the declaration part of an architecture we usualy have COMPONENT declarations and SIGNAL declarations
  • A component declarations specifies which components we want to use in our design. If we use a component several times (we instantiate a component several times), we declare it only once !
  • A component is associated with an etity. More exactly, with an entity-architecture pair (an entity and one of its architectures)
  • If the component and the entity have the same name and the same ports and generics, then the association (binding) between the component and the entity is implicit (it is realised by the simulator by default). If they have different names, then we have to write a configuration. We will try to avoid this situation.
  • Signals declared in the declaration part of the architecture struct will connect the output of the internal gates (components, in general) with the input of other internal gates (i.e., components), like in figure 15.
  • In VHDL it is not allowed to connect directly an input port of a component with the output port of another component, so we have to use signals for connecting them.
  • But we can connect an input port of the entity that we model with an input port of an internal component,
  • Or an output port of an internal component with an output port of the modeled entity.
  • Inside a structural architecture we use component instantiation statements.
  • The syntax of a component instantiation statement is the following:
    1. The statement must have a label (most VHDL statements can have a label, but for majority of them, the label is not mandatory). Labels must be different inside an architecture, i.e., each component instantiation statement must have a different label.
    2. After the label there is the component name, the same like in the component declaration (from the package components in our case)
    3. Then there can be the generic map clause, not shown here. The generic map clause can be used in order to change the value of a generic parameter.>
    4. And the port map clause
  • The port map makes the association between the formal ports and the actual ports
  • The formal ports are the ports from the component declaration
  • The actual ports are the signals that are connected to the ports of the component
  • An actual port can be the port of the entity that we model (see above)
  • The type of a formal port and of its corresponding actual port must correspond

  Data-flow descriptions

  • Since the structural descriptions are in general less intuitive, and quite error-prone, we will try to replace them, whenever possible, by data-flow descriptions.
  • We will replace the simple circuits, like gates, by their logic expressions.
  • A gate will be replaced by a signall assignment statement like:
    signal <= logic_expression AFTER delay;
    
  • where
    • "signal" is the signal connected to the output of the gate:
    • "<=" is the signal assignment symbol
    • logic_expression is the logic expression of the gate, i.e., the output as a logic function of the inputs
    • "delay" is the delay of the gate (in most cases we will conisder it to be 10 ns)
  • We can replece an OR gate with inputs a1 and a2 and the output s0 by:
    s0 <= a1 OR a2 AFTER 10 ns;
  • We can replace the NAND gate with inputs a, b, and c and output f by:
    f <= NOT(a AND b AND c) AFTER 10 ns;