Lab1: VHDL

A behavioural VHDL model of a 2:1 multiplexer

• We will illustrate the basic notions of VHDL using the multiplexer circuit described in Figures 13, 14 and 15, the first lecture.
• In this laboratory we will use the switch model of a multiplexer (Fig 13 from the first lecture) in order to obtain a VHDL behavioural (or sequential) description of a multiplexer
• In the next lab we will present a VHDL structural description and a data flow description of the same multiplexer circuit and we will compare the these descriptions.
• A behavioural description is a high-level description of a circuit, being more abstract than a structural description of the same circuit.
• The VHDL code that contains a high-level desription of a 2:1 multiplexer and a test bench for it can be found here (the multiplexer) and here (the testbench)
• Each circuit that is modeled in VHDL must have an ENTITY declaration, or, in short, entity
• The name of our entity is mux2_1, because we describe a multiplexer (mux) with 2 data inputs (called a and b), and one output, called z. There is another input, called s, whcih is the selection input (will be expalined).
• The interface of an entity consists of GENERIC parameters and PORTs.
• In this example, the generic parameter is called delay, is of type TIME, and is initialized with the value 20 ns (nano seconds). It specifies the delay of the multiplexer.
• Ports a,b and s are of mode IN (they are input ports), while port z is of mode OUT (output port).
• All ports of entity mux2_1 are of type BIT, but in VHDL a port can have (almost) any type
• Type BIT is predefined in VHDL and has the values '0' and '1'.
• The value '0' corresponds to logic zero, while the value '1' means logic one.
• The entity declaration ends with the keyword END optionally followed by the keyword ENTITY and, also optionally, by the name of the entity
• In order to specify what an entity does or how it is implemented, we need an ARCHITECTURE BODY (or, simply, ARCHITECTURE)
• An entity can have any number of architecure bodies !!
• In VHDL we can have behavioural modelling (called also sequential modelling style), and structural modelling style. There is also a third modelling style, called dataflow modelling.
• After the keyword ARCHITECTURE we have the name of the architecture and the name of the corresponding entity. Here, the name of the architecture is behave, because it is a behavioural description.
• Then it follows the declaration part of the architecture, before the keyword BEGIN
• In this architecture there are no declarations, only a comment.
• In VHDL a comment starts from the symbol "--" till the end of the line. There are no block comments.
• Between the keywords BEGIN and END [ARCHITECTURE] there is the body of the architecture
• Here the symbol [ ] means optional
• The statements situated in the architecture body are concurrent: they are executed in the same time, hence the order in which they are written is not important.
• In this example, we have only one statement, aprocess statement, because we heve a behavioural description.
• Behavioural description means with processes.
• The statement PROCESS is a composed statement.
• The statement PROCESS itself is a concurrent statement, but the statements inside the PROCESS (between BEGIN and END PROCESS) execute sequentially.
• In this example, the code inside process is self-explaining:
  • If the selection input s has the value '0' (IF s='0' ), the output z will receive the value of the input a after the time delay (20 ns).
  • Else (i.e, if s='1'), the output z will be assigned the value of the input b after the time delay.
  • The process repeats every time when at least one of the signals from the sensitivity list of the process changes its value. The sensitivity list of a process is written between parenthesis, after the keyword PROCESS.
  • The sensitivity list of this process consists of the signals a, b and s.
• In general a PROCESS can have either sensitivity list, or WAIT statements.

The test bench

• In this example, the top-level entity is called test_bench, and it has no input ports (it has no ports at all, but the important thing is that it has no input ports !).
• The architecture (here it is named struct) contains an instantiation statement (called direct instantiation), of our entity, where we specify what signals are connected to the ports of the entity mux2_1 (having the architecture behave).
• This statement must have a label. Here the label is label1. If inside an architecture there are several instantiation statements, each one must have a different label.
• We will give more details about the instantiation statement when we will discuss the structural modelling.
• The signals a_s, b_s, s_s and z_s are declared as internal signals in this architecture, and they are connected to the ports of the entity using the clause PORT MAP from the instantiation statement.
• The other 3 statements in the architecture are processes and they are used to give values to the signals a_s, b_s, and z_s, connected to the inputs of the entity mux2_1.
• We expect to see at the signal z_s, connected to the output z of the multiplexer, the value of the signal a_s for the time interval when s_s is '0', and the value of the signal b_s for the time interval when the signal s_s is '1'. Also, we expect to see the 20 ns delay (the input-output delay of the multiplexer).
• To implement this test scenario, we keep the signal s_s with value '0' for a long period of time (for example, 1000 ns) and then an equal amount of time we keep it wit value '1'.
• This is implemented by the process with the label s_s_proc.
• In order to make a clear distinction between the signals a_s and b_s, we implement each of them as a periodic signal, but the period of b_s is twice as much as the period of a_s:
• the period of a_s is 80 ns (the signal has the value '0' for 40 ns, then the value '1' for the next 40 ns, and this sequence is repeated).
• This is implemented by the process a_s_proc.
• In a similar way, the process labeled b_s_proc generates the signal b_s, with a period of 160 ns (80 ns on '0' and 80 ns on '1').
• Here we have to simulate the entity test_bench with the the architecture struct.