Lab10: Latches and flip-flops simulated in VHDL

Simulate the following latches and flip-flops, described in Lecture 6 "Sequential Logic Design Principles.Latches and Flip-Flops":

S-R latch with enable (fig 13)

D latch (fig 15)

Edge-triggered D flip-flop (fig 18)

Edge-triggered J-K flip-flop (fig 31)

Edge-triggered T flip-flop with Enable (fig 34)

Edge-triggered D flip-flop with enable

Edge-triggered D flip-flop with scan

You can start from the VHDL code for the R-S latch circuit, that can be found here:

Two NOR gates with feedback loop

You may also use the VHDL code that describes behaviourally the SR latch, the D flip-flop and the J-K flip-flop with reset and set, that can be found here:

latches and flip-flops and a test for latches and flip-flops