Description of the VHDL code for the circuit from figure 15

Entity and behavioural architecture

• The entity declaration mux2_1 and the architecture behave are the same like in Lab1.

A structural style architecture body for mux2_1

• In general, in the declaration part of the architecture struct we usualy have COMPONENT declarations and SIGNAL declarations
• In order to simplify the coding, we declared all the components that we need in the package components from the file components.vhd , hence we declare only the internal signals here (in the declaration part of the architecture).
• The components from the package components end the entities from the file gates.vhd can be associated by default (without configuration).
• The file gates_plus.vhd, which contains the entities of the gates and their architectures, and the file components.vhd, which contains the package components mulst be downloaded into the working directory and then compiled.
• In order to make the content of the package visible inside the architecture struct, we have to put an use clause:
  
  USE WORK.components.ALL;
  
  before the architecture, or before the entity declarations. In our code is before the architecture.
• Signals declared in the declaration part of the architecture struct will connect the output of the internal gates (components, in general) with the input of other internal gates (i.e., components), like in figure 15.
• In VHDL it is not allowed to connect directly an input port of a component with the output port of another component, so we have to use signals for connecting them.
• But we can connect an input port of the entity that we model with an input port of an internal component,
• Or an output port of an internal component with an output port of the modeled entity.
• In this example, we have only component instantiation statements, because we have a structural description.
• The syntax of a component instantiation statement is the following:
  1. The statement must have a label, followed by the name of the component, then the generic map clause and the port map clause.
  2. The port map makes the association between the formal ports and the actual ports
  3. The syntax of VHDL permits two types of associations:
     1. positional association: when we write the name of the actual port on the corresponding position of the formal port (the name of the formal port does not appear). Avoid using it, because it can generate errors that are very difficult to debug !
     2. named association: syntax is: formal_port => actual_port
  4. We used here named association
  5. For example, if we take the statement:
     
     and1: and2gate PORT MAP(X => a, Y => sn, F => asn);
     
     the label is and1, the component name is and2gate, and the PORT MAP clause specifies that the input port X of the component and2gate is connected to the signal a (the input port of the entity mux2_1), the input port Y of the component is mapped (i.e., connected) to the internal signal sn, while the output F of the gate (of the component) is connected to the internal signal asn.
  6. Using positional association, the same component instantiation can be written:
     
     and2: and2gate PORT MAP(a, sn, asn); -- positional association
     
     
  7. As an exercise, draw the circuit diagram from the VHDL code in order to check the correctness of the code.

A dataflow style architecture body for mux2_1

• We will use this style of modeling in order to replace each gate with its logic expression.
• In this way we can avoid writting structural description, and replace them with data flow description, with an identical functioning.
• For data flow descriptions, we do not need to declare components, hence we do not need the file components.vhd which contain the package components.
• Also, we do not need the descriptions of the gates (their entities and architectures), which means that we do not need the file gates_plus.vhd.
• We do need to declare internal signals in the declaration part of the architecture.
• The body of the architecture will contain the signal assignment statements which replace the component instantiation statements.
• For a realistic implementation, each component instantiation statement representing a gate will be replaced with the signal assignment statement corresponding to the logic expression of that gate.
• For example, we replace the statement:
  
  and1: and2gate PORT MAP(X => a, Y => sn, F => asn);
  
  with:
  
  asn <= a AND sn AFTER 10 ns;
  
  
• And similar for all the statements from the architecture struct.
• In this way we will obtain exactly the same behaviour of the multiplexer, but with a more comprehensible code.