Description of the test bench

In order to verify the correctness of a modelled circuit, we have to put the circuit in a test bench, where we give all possible input combination (if possible), or at least a relevant set of input combinations, and verify the outputs

Entity

Entity test_bench is the same like in Lab1.

Architecture

The architecture can be a pure structural description, but in general there can be also concurrent signal assignment statements, for manually generating input values. Here is the second situation.
The name of the architecture is struct, and this architecture is an enhancement of the test bench architecture from the first lab.
The declaration part of the architecure contains the declaration of the signals a_s, b_s, s_s, and z_s, like in lab1. The signals a_s, b_s, s_s will be connected to the inputs of the circuits that we want to test.
Since we want to test 3 circuits, each circuit with one output signal, it means that we need, for each of the 3 circuits, a signal to be connected to the circuit's output.
In VHDL it is not allowed to connect together the outputs of more than one circuit (except for the resolved signals, will NOT be discussed !).
Hence, we declared two more signals, z2_s, and z3_s, to connect them to the outputs of the second and third ciruits.
The circuits that we test are the 3 different implementations (i.e., the 3 different architectures) of the entity mux2_1.
So, in the body of the architecture we have 3 different instantiations of mux2_1, each instantiation with a different architecture.
In this way we will compare the 3 architectures and see if they work in the same way.
We use the same simulation scenario, like in lab1, we make signals s_s, a_s and b_s to oscilate with different time periods.

The simulation results

If we look at the waveforms produced by the simulator, we see that the signals z_s, z2_s andz3_s are all identical, with an exception between the simulation moments 1020 ns and 1030 ns, when, for 10 ns, the signals z2_s and z3_s have the value '1', while z_s is '0'.

A detailed explanation will be given when we will discuss hazards.

For now, we can see from Fig 15 that, from input s to the output z, there are two different paths, with a differen number of circuits:

the "upper path": s -> invgate -> sn -> upper and2gate -> asn -> or2gate -> z
the "lower path": s-> lower and2gate -> sb -> sb -> or2gate -> z

On the upper path there is one more gate (the invgate) compared to the lower path.

This makes that for 10 ns, between the moment 1010 ns, to the moment 1020 ns, both paths from the data inputs (a and b) to the output z are open in the same time. Normally, only one path should be open at any time.

Because of that, the output z will have the value '1', instead of '0', between the moments 1020 ns and 1030 ns.

It means that the structural description and the data-flow description are the most realistic ones, being closer to reality than the sequential description.

In conclusion, the data-flow description is as realistic as the structural description, but the code is more understandable and less error-prone.