Lab7: Hazards simulated in VHDL

• Simulate the circuit from Figure 15, lecture 4, with 1 inverter, two 2-inputs AND gate, one 2-inputs OR gate (transformed in one 3-inputs OR gate)
• You can find the necessary VHDL code here:
  • Gates, circuit for static 1 hazard and test bench
• Then modify the ciruit in order to remove the hazard, according to figure 18, page 59, lecture 4.