Lab 8 and 9: Combinational circuits: multiplexers, decoders, programmable logic devices

Problems for lab 8:

1. From problem 1, "Decoders and multiplexers", solve on paper all 9 exercises (except number 6), then, using the circuit diagram, write in a HDL the structural description of the circuits that you designed (except exercises 5 and 6).
2. From problem 2, "Expanding decoders and multiplexers", solve (on paper and by simulation) exercise 1 and 2. For simulation, use the circuits modeled in VHDL or Verilog at problem 1, in order to expand them.
3. From problem 3, "Implementing functions with combinational circuits", solve only exercise 1 on paper, then simulate the resulted circuit.

1. Decoders and multiplexers

   1. Realize the truth table and the circuit diagram of a 2-to-4 decoder with active-high data inputs, active-high data outputs, one active-high enable input and one active-low enable input.
      
      Hint: Circuit diagram means with gates.
      
      
   2. Realize the truth table and the circuit diagram of a 3-to-8 decoder with active-high data inputs, active-low data outputs, one active-high enable input and one active-low enable input.
   3. In figure 6.35 from slide 34 (lecture 5 "Combintational Circuits: Multiplexers, Decoders, Programmable Logic Devices"), explain the "extra" inverters on inputs A, B and C.
   4. Realize the circuit diagram for 2:1 and 4:1 generic multiplexers.
   5. Implement a 2:1 multiplexer using only tri-state buffers.
   6. ** Implement a 4:1 multiplexer (MUX) using tri-state buffers, and a small number of gates, if needed.
   7. Realize the truth table and the circuit diagram for a 4:1 multiplex with one active-high enable input and one active-low enable input.
   8. Realize the truth table and the circuit diagram for a 8:1 multiplex with one active-high enable input and one active-low enable input.
      
      Hint: When you make the truth table of a multiplexer, DO NOT use separate columns for the data inputs. Use columns only for control inputs, otherwise you will have a very big (maybe too big) truth table ! See, for example, table 5-34 from slide 48. In table 5-34, control inputs are C, B and A, the data inputs are D0, D1, D2, ..., D7, and there is one enable input, named EN_L. The termination "_L" means that it is active-low, see table 5.1 from slide 90.
      
      
   9. Implement a 1:4 demultiplexer with one data input active-high, two control inputs active-high and four data outputs active-high, using AND, OR and NOT gates.

2. Expanding decoders and multiplexers:

   For this kind of problems, use block diagram (with boxes, not with gates!) for decoders, multiplexers, etc. Do not draw each circuit at gate level.
   
   
   1. Expand the 2-to-4 decoder from problem 1, in order to obtain a 4-to-16 decoder.
   2. Realize the block diagram of a 5-to-32 decoder using only 3-to-8 decoders.
      
      
   3. Expand 2:1 multiplexers in order to obtain a 8:1 multiplexer using:
      1. Multiplexers, a decoder and a gate (for connecting the outputs)
      2. Only multiplexers. Hint: see figure 9.36 (b) from slide 58. If you ignore the function generators (the FG boxes from figure), you see a tree of muxes. Use this idea in order to solve the problem.

3. Implementing functions with combinational circuits.

   1. Implement three function of variable A, B and C using a 3-to-8 decoder and a small number of gates. The functions are:
      • F from problem 2 a) from lab 5 (Karnaugh maps),
      • the function G = A'B'C' + A'BC' + ABC
      • the function H = AB + BC (By ABC we mean A and B and C)
   2. Take the function F from problem 1 f) from lab 5 and 6, and expand it on the variable A (the most significant), using Shannon's expansion theorem. You will obtain two functions, named F0 and F1, both of varibales B, C and D. Implement the two functions using:
      • a ROM memory (of 8 words, each word having 2 bits). When you represent the ROM memory, do it like in figure 9-23 from slide 70, not like in figure 9-20 from slide 66.
      • a PLA. For PLA implementation you have to mininize the two functions first. Represent the PLA like in fig 9-26 from slide 78, or like in fig 9-27 b from slide 81, or like in table 9-1 from slide 79.
   3. Describe the output function G of a 5-bit prime number detector using the variables N4, N3, N2, N1, and N0. Expand the function on the variable N4 (the most significant), obtaining in this way the functions G0 and G1. Implement the two functions using:
      • A ROM memory of 16 words, each word consisting of 2 bits.
      • A PLA.

4. Exclusive OR gates

   1. Represent the truth table of the function of four variables G(W,X,Y,Z) = W XOR X XOR Y XOR Z.
   2. Represent the function G(W,X,Y,Z) from previous problem on a Karnaugh map and compare it with the fucntion F(W,X,Y,Z) from problem 2 e) from lab 5.