The test bench

• When we write a computer program, in any programming labguage, we want to test that the program works "correctly" (i.e., as we expect).
• In order to do this, we give different inputs to our program, ideally all possible input combinations, and analyze the outputs of the program.
• In many situations it is not possible, or not feasible, to give all input combinations, so we have to create different scenarios in order to test the functionality of our program or circuit.
• An experienced designer will create relevant simulation scenarios.
• Many VHDL simulators do not provide the possibility to give the inputs of a program in an interactive manner (i.e., from the keyboard).
• In other words, the top-level entity must not have input ports.
• In consequence, when we want to test the functionality of a VHDL model of a circuit or of a system, we have to put our circuit in a testbench, and to give its inputs as VHDL code.
• A general test bench for a combinational circuit will generate all possible input combinations for this circuit.
• In order to do this, we use the files the test generator and the general testbench.
• The entity test_bench_gen, which is the entity corresponding to the general test bench, has no input ports (and no output ports in this case !).
• Here we illustrate the testbench for testing the entity mux_2_1.
• The Test Generator generates all possible input combinations for a combinational circuit with any number of inputs of type BIT.
• Hence, the TestGenerator generates all possible values for arrays of size bits, i.e., its output is
  port(value: out bit_vector((size-1) downto 0)) .
• The size of the signal named value is given by generic map in the component instantiation statement labeled tg: from the file test_bench_gen.vhd. In this example, the size will receive the value 3, because the tested entity has 3 inputs.
• The signals s_s, a_s and b_s, which are connected to the inputs of the entity mux_2_1 are mapped to the signals value(2), value(1) and respectively value(0) (the outputs of TestGenerator).
• In this way, all the 8 input combinations, i.e.: "000", "001", ...,"110", "111" will be given to the inputs of the multiplexer.
• We can compare the values of the multiplexer's inputs and output with the truth table of the multiplexer, shown in figure 14, lecture 1.
• In this case we simulate the entity test_bench_gen with architecture struct.
• A similar approach can be applied for any combinational circuit, not only for the mux_2_1.