Lab2: VHDL

More architectures for the 2:1 multiplexer

• We will show two more atchitectures for the entity mux2_1, coresponding to a 2:1 multiplexer
• We will describe and simulate the circuit shown in Figure 15, the first lecture.
• You can find the necessary VHDL code here:
  • Gates needed for further VHDL models
  • The components needed for further VHDL models
  • The file lab2_design.vhd, containing a behavioural, a structural, and a data flow description of the circuit mux2_1
  • The test bench of the circuit (the file lab2_testbench.vhd)
• After you create the working library WORK in your working directory, download in the working directory the VHDL code from the files gates_plus.vhd and components.vhd, and compile the two files.
• Then download and then compile the file lab2_design.vhd and then the file lab2_testbench.vhd
• Then simulate the architecture struct of the entity test_bench.
• Run the simulation for at least 2500 ns and look at the waveforms. What do you observe ?
  
  
• Some explanations about the code:
  
  • Description of the circuit
  • Description of the test bench
• Read A description of a general testbench in VHDL
• Download the files which contains a the test generator and a general testbench
• Modify the file which contains the test bench in order to test the dataflow (and the struct architectures of the entity mux2_1.
• Compile the two files and simulate the entity test_bench_gen.
• Compare the results of the simulation with the truth table of the 2:1 multiplexer from Lecture 1 , figure 14.
• Using the example of mux2_1 from Figure 15, use VHDL in order to simulate the generic 2-to-4 decoder with enable from Figure 6.32, page 30, lecture 6 and 7 Combintational Circuits: Multiplexers, Decoders, Programmable Logic Devices