CAD

Time table

• Lectures: Wednesday, 8-10, room A204.
• Labs: Thursday 10-12, 12-14 and 14-16, all in P17 (ASPC)

Exam 2026-2027

Syllabus

The syllabus of the CAD course in Englih and in Romanian.

Lectures 2026-2027

1. Introduction ppt and pdf
2. VHDL: Design units ppt and pdf
3. VHDL: Behavioural modelling ppt and pdf
   VHDL: Finite State Machines ppt and pdf
   
   Examples: Moore FSM, Mealy machine, clock generator and test bench
   Moore FSM implemented with one process
   Mealy FSM implemented with two processes
   Clock generator
   Test bench
4. VHDL: Data flow modelling ppt and pdf
5. VHDL: Structural description. Configurations ppt and pdf
6. (Optional:) VHDL: Subprograms. Overloading ppt and pdf
   Conversion using look-up table (more efficient than a function call)
7. VHDL: Advanced topics ppt and pdf
   Example of multiplexer implemented with guarded signals (slightly modified from the lecture notes), containing also the resolution function. And an example of disconnecting guarded signals after some delay
8. Network simulation ppt and pdf
   Confidence intervals docx or pdf
   
9. Quality of Service (QoS) in Internet ppt and pdf
10. Mobile Communication Systems: Wireless transmission ppt and pdf
11. An Introduction to Mobile Communications Systems ppt and pdf
    

The CAD grade

• You will obtain a Lab grade and an exam grade. The CAD grade will be the average of the two grades (lab grade and exam grade), if both of them are at least 5.

Lab works

Assignments

1. VHDL assignments:

   • VHDL assignments for maximum 10 out of 10 points:
     1. A simplified model of a microprocessor (uP) or of a microcontroller (uC). Details
     2. A register transfer level (RTL) implementation of a multiplication or division algorithm in fixed point arithmetic (e.g. Robertson, Booth, restoring or non-restoring division). Details
     3. Serial data transmission and reception using error detecting and correcting codes. Details
     4. A circuit from the family of the 80x86 uP: 8253 or 8255. A simplified RTL model of the circuit will be realized.
     
     
   • Simplified VHDL assignments, a maximum of 9 out of 10 points:
     1. A simplified model of a multiplication or division algorithm in fixed point arithmetic. You will implement a known multiplication algorithn (e.g. Robertson, or Booth), or a division algorithm (e.g. restoring or non-restoring). The model will have two components: a control unit (CU), implemented as a FSM (Finite State Machine), and an execution unit (EU), each of them described behaviourally. EU performs all operations on the operands (right or left shift, addition, etc), and the CU gives the commands for the EU.
        
        
   • Simplified VHDL assignments for a maximum of 6 points:
     1. A simplified model of a multiplication or division algorithm in fixed point arithmetic. You will implement a known multiplication algorithn (e.g. Robertson, or Booth), or a division algorithm (e.g. restoring or non-restoring). The model will have one component: a control unit (CU), implemented as a FSM, described behaviourally.
        In this implementation CU performs all operations on the operands (right or left shift, addition, etc).
     2. A simplified patient state monitoring device. The patient can be in one of the states: VB (very bad), B (bad), A (average), G (good) and VG (very good). The system reads the value of a parameter of the patient, and, based on that value, the state of the patient will improve, will remain the same, or it will be worse.
     3. A finite state machine (FSM) reads a number between 0 and 99. The number can be a very small (VS) number, a small number (SN), a medium number (MN), a large number (LN), or a very large number (VL). The states of the system can be: INIT (initial state), VS (very small), S (small), M (medium), large (L), and VL (very large). Imagine the state transition table of the FSM, starting from the state transition table of the FSM given in table I from this paper .

     In all cases you will have to test the functionality of the model.
     
     A 100% "software implementation" (i.e, without hardare components that communicate) of a multiplication or division algorithm will NOT be accepteed !
     
     

2. OMNeT++ assignments:

   
   Using the open source network simulator OMNeT++, make a simulation model for one of the following systems:
   
   
   • OMNeT++ assignments for a maximum of 10 points:
     1. A scheduling model at MAC level for LTE, downlink (DL) transmission. You can find a more detailed description of the problem here .
     2. A scheduling model for a radio system with location dependent errors. A more detailed description of the problem is given here
     3. A scheduling model for 5G. It is an extension of the scheduling model for LTE. More details can be found here
        
     4. A vertical handover (VHO) model. Details here
        
   • OMNeT++ assignments for a maximum of 9 points:
     1. A token bucket - based meter and marker system for IP packets. Details.
        
     2. A scheduling model for an IP packets scheduler placed on a DiffServ node. Details.
        
   
   
   The simulator can be downloaded from http://www.omnetpp.org ,where you can find also documentation, tutorials, examples, etc.
   
   
3. A presentation of a scientific paper from a given list
   • The list is given on the web page of the Cellular Data Network course
   • You need username and password to access this page. They are:
     • username: mcs
     • passwd: mcs05
   • You have to make a presentation of approx 30 minutes from that paper
   • and to answer the questions related to the presentation and to the paper.

The deadline for the lab assignment is December the 17th, 2026, 4 PM. After that, delay penalties will be applied !

The assignment (the code) must be uploaded on Virtual Campus at least 48 hours before the presentation.

It is not allowed to copy the assignment(s) or parts of the assignemnt(s) from colleagues, from Internet or from other sources. By doing so you will NOT promote the CAD laboratory !!

You have to mention if you have code realised by, or in collaboration with ChatGPT or another AI software. It is not allowed to realise ALL code with AI !!!