CAD

Exam 2024-2025

1. First presentation: , room ,
2. Second presentation: , room

Syllabus

The syllabus of the CAD course in Englih and in Romanian.

Lectures 2024-2025

1. Introduction ppt and pdf
2. VHDL: Design units ppt and pdf
3. VHDL: Behavioural modelling ppt and pdf
   VHDL: Finite State Machines ppt and pdf
   
   Examples: Moore FSM, Mealy machine, clock generator and test bench
   Moore FSM implemented with one process
   Mealy FSM implemented with two processes
   Clock generator
   Test bench
4. VHDL: Data flow modelling ppt and pdf
5. VHDL: Structural description. Configurations ppt and pdf
6. Optional: VHDL: Subprograms. Overloading ppt and pdf
   Conversion using look-up table (more efficient than a function call)
7. VHDL: Advanced topics ppt and pdf
   Example of multiplexer implemented with guarded signals (slightly modified from the lecture notes), containing also the resolution function. And an example of disconnecting guarded signals after some delay
8. Network simulation ppt and pdf
9. Quality of Service (QoS) in Internet ppt and pdf
10. Mobile Communication Systems: Wireless transmission ppt and pdf
11. An Introduction to Mobile Communications Systems ppt and pdf
    Optional: GSM and GPRS pptx and pdf

The CAD grade

• You will obtain a Lab grade and an exam grade. The CAD grade will be the average of the two grades (lab grade and exam grade), if both of them are at least 5.
• The written exam can be replaced by points obtained for the assignments (VHDL assignment, OMNeT++ assignment, or both).
• The points at CAD (CAD_points) will be computed as follows:

  CAD_points = 1 + lab_works_points + VHDL_assignment_points + Omnet_assignment_points
  

• The points for the mandatory lab works (i.e., lab_works_points) will always be included in the lab grade.
• The points obtained for the VHDL assignment, or for the Omnet assignment, or for both of them, can be split between the lab grade and the exam grade, at the student's choice.
• In order to obtain points for the VHDL assignment, your VHDL code should compile and you should be able to simulate it.
• In order to obtain points for the Omnet++ assignment, your code should compile and you should be able to simulate it. Also, the simulation must run a certain amount of time (ideally, it should be able to run as much as required !)
• Each assignment can be realised by groups of two students or by a single student.
• The code of the assignment should be uploaded on Virtual Campus.
• The assignment should be presented and the students are expected to answer questions.
• If the assignment is realised by 2 students, they could obtain different grades !

Lab works

Assignments

VHDL assignments:

• VHDL assignments for maximum 10 out of 10 points:
  1. A simplified model of a microprocessor (uP) or of a microcontroller (uC). Details
  2. A register transfer level (RTL) implementation of a multiplication or division algorithm in fixed point arithmetic (e.g. Robertson, Booth, restoring or non-restoring division). Details
  3. Serial data transmission and reception using error detecting and correcting codes. Details
  4. A circuit from the family of the 80x86 uP: 8253 or 8255. A simplified RTL model of the circuit will be realized.
  
  
• Simplified VHDL assignments, for maximum 8 out of 10 points:
  1. A simplified model of a multiplication or division algorithm in fixed point arithmetic. You will implement a known multiplication algorithn (e.g. Robertson, or Booth), or a division algorithm (e.g. restoring or non-restoring). The model will have two components: a control unit (CU), and an execution unit (EU), each of them described behaviourally. EU performs all operations on the operands (right or left shift, addition, etc), and the CU gives the commands for the EU.
  2. A simplified patient state monitoring device. The patient can be in one of the states: VB (very bad), B (bad), G (good) and VG (very good). The system reads the value of a parameter of the patient, and, based on that value, the state of the patient will improve, will remain the same, or it will be worse.
  3. A finite state machine (FSM) reads a number between 0 and 99. The number can be a small number (SN), a medium number (MN), or a large number (LN). The states of the system can be: INIT (initial state), S (small), M (medium), and L (large). The state transition table of the FSM is given in table I from this paper .

  In all cases you will have to test the functionality of the model.

OMNeT++ assignments for a maximum of 10 points:

1. A scheduling model at MAC level for LTE, downlink (DL) transmission. You can find a more detailed description of the problem here .
2. A scheduling model for a radio system with location dependent errors. A more detailed description of the problem is given here
3. A scheduling model at MAC level for LTE, uplink (UL) transmission. Details here
   
4. A scheduling model for 5G. It is an extension of the scheduling model for LTE. More details can be found here
   
5. A vertical handover (VHO) model. Details here
   

OMNeT++ assignments for a maximum of 8 points:

1. A token bucket - based meter and marker system for IP packets. Details.
   
2. A scheduling model for an IP packets scheduler placed on a DiffServ node. Details.
   The simulator can be downloaded from http://www.omnetpp.org ,where you can find also documentation, tutorials, examples, etc.
   
   

   The deadline for the lab assignment is December 13, 2024. After that, delay penalties will be applied !

   It is not allowed to copy the assignment(s) or parts of the assignemnt(s) from colleagues, from Internet or from other sources. By doing so you will NOT promote the CAD laboratory !!