Digital Logic

Timetable

• Lecture: Tuesday 10-12, room A2, Faculty of Chemistry (Doru Todinca)
• Labs, room P17, ASPC:
  • Wednesday 8-10, 10-12, 12-14 (Doru Todinca)
  • Thursday 8-10, 10-12 (Claudiu Tirisi)

All missed labs should be re-worked, in order to promote the Digital Logic lab ! Week 14 is only for re-works.

Lab_grade = ROUND((test1_grade + test2_grade + test3_grade + test4_grade)/4 + points_for_activity )

• test_1 is from Karnaugh maps
• test_2 is from combinational circuits
• test_3 is from latches and flip-flops
• test_4 is from clocked synchronous state-machines

Syllabus

The syllabus of DL course in Englih and in Romanian.

Lectures

• Lecture 1. Introduction
  • Optional: CMOS Logic Family. Several CMOS Gates
• Lecture 2. Combinational Logic Design Principles. Switching algebra
  • Two examples of circuits which contain a feedback loop
• Lecture 3. Combinational Logic Design Principles. Combinational Circuits Analysis and Synthesis
• Lecture 4 and 5. Combinational Logic Design Principles. Combinational Circuits Synthesis Using Karnaugh Maps
• Lecture 6 and 7. Combintational Circuits: Multiplexers, Decoders, Programmable Logic Devices ppt and pdf
• Lecture 8 and 9. Sequential Logic Design Principles. Latches and Flip-Flops
• Lecture 10. Sequential Logic Design Principles.Clocked Synchronous State-Machine Analysis and Synthesis
  More examples of clocked synchronous state machines
• Lecture 11 and 12. Sequential Logic Design Principles.Clocked Synchronous State-Machine Synthesis (Continued)
• Lecture 13. Sequential Logic Design Practices

Laboratory